SUBJECT OUTLINE 48561 Power Electronics and Drives Course area
UTS: Engineering and Information Technology
Delivery
Autumn 2014; City
Subject Field of practice: Electrical Engineering major classification Credit points 6cp Requisite(s)
48531 Electromechanical Automation
Result type
Grade and marks
Subject coordinator Associate Professor David Dorrell O: CB1.24.20D T: x24245 E: david,dorrell@uts,edu.au
Teaching staff Lab demonstrator Mr. William Song, O: CB01.23.14, T: 0422 153 515, E:
[email protected]
Subject description The objectives of this subject are to enable students to: acquire an understanding of the nature of power semiconductor devices and their control and use in switch-mode; understand the arrangement and topology of the circuits in which switch-mode devices are used; appreciate the use of power electronic circuits in high-power applications such as motor drives; be aware of the electromagnetic interference problems associated with power electronic systems; use commercial software for the rigorous circuit analysis of real power electronic systems; analysis and design circuits to meet specific specifications; and fabricate basic power electronic circuits such as a chopper. Topics include: topology and switching characteristics for IGBT, MOSFET, GTO, Thyristor and other devices; gate drive circuit requirements; power conversion circuits including DC-DC choppers, AC-DC controlled rectifiers, and DC-AC inverters; pulse-width modulation techniques; snubbers and thermal design for power devices; voltage and current controlled inverters; applications such as switch-mode power supplies, DC drives, AC drives, UPS systems, HVDC; recent advances in device technology; control techniques; and EMC and electromagnetic interference.
Subject objectives Upon successful completion of this subject students should be able to: 1. Show awareness of the impact of power electronic circuits on utility supply; 2. Meet the criteria of open-ended and design-oriented labs, and be able to justify the design; 3. Analyze and evaluate the merits and disadvantages of large power electronic systems; 4. Read and understand datasheets of power electronic devices and related ICs; 5. Design, analyze, model, build and test the operation of simple power electronic circuits in a lab environment; and 6. Be skillful in technical writing and presentation of electrical machine technology and teamwork skills through the laboratory work and assignment.
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This subject also contributes specifically to the development of the following course intended learning outcomes: Identify, interpret and analyse stakeholder needs. (A.1) Identify constraints, uncertainties and risk of the system (social, cultural, legislative, environmental, business etc.) (A.3) Identify and apply relevant problem solving methodologies (B.1) Design components, systems and/ or processes to meet required specification (B.2) Implement and test solution (B.5) Demonstrate research skills (B.6) Develop models using appropriate tools such as computer software, laboratory equipment and other devices (C.2) Evaluate model applicability, accuracy and limitations (C.3) Reflect on personal and professional experiences to engage in independent development beyond formal education for lifelong learning (D.2) Communicate effectively in ways appropriate to the discipline, audience and purpose. (E.1) Work as an effective member or leader of diverse teams within a multi-level, multi-disciplinary and multi-cultural setting (E.2)
Teaching and learning strategies Class time is 2 hours per week. This include lectures, worked examples and introduction to the project Worked examples will be given in class but students are expected to work through tutorial questions themselves and not expect them to be done for them in class. There are three 3-hour lab sessions. Time will be allocated to discuss project and problem solving with students on an individual or small group basis. The focus of learning and teaching strategy is to: Present the information in a structured manner with interactive discussion Present practical problems for classroom discussion Reinforce student learning through project work The lab exercises are oriented towards analysis. The project is oriented towards developing and testing the skill of students to research an application then apply computer-based programs to model and analyse power electronic systems.
Content Areas of use of Power Electronics Power electronics Devices Analysis and design of Boost Converter Analysis and design of Buck Converter Flyback Converter Operator and Analysis Controlled Rectifier circuits: Understanding and analysis Single-phase and three-phase inverters Harmonics in Power electronic circuits DC drives and AC drives
Program Week/Session
Dates
Description
1
24 Feb
Lecture 1: Subject overview, Introduction, Simulation methods for power electronics
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2
3 Mar
Lecture 2: Devices Introduce simulation methods Notes: Announce Group allocation
3
10 Mar
Lecture 3: DC to DC converters 1 Introduce design project and discuss requirements.
3
13 Mar
Group 1 Lab 1 Other groups - consultation time
4
17 Mar
Lecture 4: DC-DC converters 2
4
20 Mar
Group 2 - Lab 1 Other groups - consultation time
5
24 Mar
Lecture 5: Switching DC power supplies Work on simulation and projects
5
27 Mar
Group 3 Lab 1 Other groups - consultation time1 Notes: Group 1 Lab 1 lab report due
6
31 Mar
Lecture 6: DC to AC converters
6
3 Apr
Group 1 - Lab 2 Other groups - consultation time Notes: Group 2 Lab 1 lab report due
7
7 Apr
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Lecture 7: Introduction to Motor Drives in the context of Power Electronics
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7
10 Apr
Group 2 - Lab 2 Other groups - consultation time Notes: Group 3 Lab 1 lab report due
8
14 Apr
Tutorial week - personal work unless overrun session arranged Notes: Group 3 Lab 1 lab report due in the 17th April
9
28 Apr
Lecture 8: Modelling and simulation of systems
9
1 May
Group 3 - Lab 2 Other groups - consultation time Notes: Groups 1 and 2 lab 2 reports due
10
5 May
Presentation evening for design projects DD away
10
8 May
Group 1 - Lab 3 No consultation - DD away
11
12 May
Lecture 9: Power electronics in power systems and loss calculations. Phase angle control.
11
15 May
Group 2 - Lab 3 Other groups - consultation time Notes: Group 3 - lab 2 report due
12
21 May
Design workshop and examples classes
12
22 May
Group 3 - Lab 3 Other groups - consultation time Notes: Group 1 Lab 3 lab report due
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13
26 May
Design workshop and examples classes Notes: Group 2 Lab 3 lab report due
14
2 Jun
Revision and past papers Notes: Group 3 Lab 3 lab report due Design project reports due
Additional information Repeated Failure in this Subject The Faculty takes repeated failures in a subject seriously and enforces Rule 10.6 of the University’s Student and Related Rules: http://www.gsu.uts.edu.au/rules/10-6.html You should read these rules and be aware of the consequences of failure. If you have failed twice before in this subject, then: (i) You must seek advice from the Subject Coordinator. You will be asked to draw up and submit a study plan that outlines your strategy for passing this subject on the third attempt. A signed copy of this study plan will be kept by the Faculty for internal records. (ii) If you do not seek advice from the Subject Coordinator by Week 2, then you do not have the Faculty’s permission to enrol in the subject. If you stay enrolled in the subject then you will be breaking Rule 10.6.2 (1) of the University’s Student and Related Rules. (iii) You need to be aware that if you fail this subject for a third time, you will need to seek permission from the relevant Program Head for any further enrolment in this subject (see below). If you fail this subject for a third time, then: (i) Subject Coordinators will deny permission for any further enrolment unless you can produce well-documented evidence that requires special consideration. In such cases, the Subject Coordinator will refer the matter to the relevant Course Coordinator, who will grant or deny enrolment for a fourth or subsequent attempt based on a student’s overall performance in the course and the extent to which extenuating circumstances have contributed to one or more of the failures. (ii) If you are granted permission for a fourth or subsequent attempt at this subject, then you must seek continuing assistance throughout this semester from the Subject Coordinator.
Field trips None
Additional subject costs Students may have to purchase components for experimental labs. However we will try to avoid this.
Assessment Assessment task 1: Lab Exercises Intent:
To analyse and verify simple power electronic circuits in order to understand the nature of switch
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Intent:
To analyse and verify simple power electronic circuits in order to understand the nature of switch mode electronic operation.
Objective(s): This assessment task addresses subject learning objectives: 2, 3, 4, 5 and 6 This assessment task contributes to the development of the following course intended learning outcomes: B.1, B.2, B.5, C.3, E.1 and E.2 Weight:
30%
Due:
Each lab report is due 2 weeks after completion of the lab or date specified in the Outline. Reports will not be accepted from students who have not completed the lab session. No extensions will be granted without due documentation and tasks from other subjects and work commitments will not be accepted.
Task:
To analyse and verify simple power electronic circuits. There will be an emphasis on understanding switch mode operation of devices and analysis of dc to dc circuits.
Further None information: Criteria Criteria linkages: Correctness of waveform representation and interpretation
Weight (%)
SLOs
CILOs
20
2, 3, 6
B.1, B.2, B.5, C.3, E.1
Correctness of calculations and analysis
20
3, 6
B.1
Justification and accuracy of test results
20
5
B.1, B.5
Completeness of Interpretation and discussion of result
20
4
B.1
Group work towards common goal
10
6
E.2
Contribution to team work (succinctness, courtesy, motivation, taking a fair share of the work)
10
6
E.2
SLOs: subject learning objectives CILOs: course intended learning outcomes
Assessment task 2: Group and individual design exercise Intent:
The aim is to design a power electronic system for an application. Students will work in groups of three and work through research, design, simulation and final reporting stages. Students will work together but present their own work in clearly defined sections of the reports submitted.
Objective(s): This assessment task addresses subject learning objectives: 1, 2, 4, 5 and 6 This assessment task contributes to the development of the following course intended learning outcomes: A.1, A.3, B.1, B.2, B.5, B.6, C.2, C.3 and E.2 Weight:
30%
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Weight:
30%
Due:
Reports are due on the last day of semester. Reports will not be accepted from students who have not completed the the design project with their team. No extensions will be granted without due documentation and tasks from other subjects and work commitments will not be accepted.
Length:
There is no restriction on length but students should be aware that plagiarism will be checked using Turnitin.
Task:
To model and analyse selected power electronic circuits using suitable software. Develop more complicated circuits for analysis. There will be several milestones (simulation write-ups to be completed during semester by due dates).
Criteria linkages:
Criteria
Weight (%)
SLOs
CILOs
Completeness of requirements specification
10
1, 2, 5
A.1
Application of theory and methodology
10
1, 2, 5
A.1, B.1
Justification of interpretation
5
2, 4, 5
A.1, C.2
Completeness of Interpretation and Discussion of result
10
2
A.1, B.1
The constraints and uncertainties in the analysis have been identified and the assumptions have been clearly stated
5
2, 4, 5
A.3, B.5
Correctness of calculation, design and simulation
30
4, 5
B.1, B.2, B.5, C.2, C.3
Accurate acknowledgement of sources
5
6
B.6
Linkage to practice and theory
5
6
B.6
Discussion and reflection on results
10
1, 2
C.3
Contribution to team work (succinctness, courtesy, motivation, taking a fair share of the work)
10
6
E.2
SLOs: subject learning objectives CILOs: course intended learning outcomes
Assessment task 3: Final examination Intent:
To assess students' understanding of the basic power electronics concepts and to test their capacity to analyse and solve problems
Objective(s): This assessment task addresses subject learning objectives: 1, 2, 4, 5 and 6 This assessment task contributes to the development of the following course intended learning outcomes: B.1, B.2, C.3, D.2 and E.1 Weight:
40%
Task:
Analysis and Solution of Problems related to Power Electronics
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Task:
Analysis and Solution of Problems related to Power Electronics
Criteria linkages:
Criteria
Weight (%)
SLOs
CILOs
Correctness of drawing
10
2, 5
B.1
Application of methodology
15
1, 2, 5
B.1
Correctness of calculations and analysis
20
2, 4, 5
B.1
Correctness of analysing problem and evaluating options
20
2, 4, 5
B.2
Justification of solution
5
1, 5
C.3
Effectiveness of time management in revising and understanding information for exam
20
1
D.2
Conciseness and relevance of information
5
2, 6
E.1
Correct usage of language
5
2, 6
E.1
SLOs: subject learning objectives CILOs: course intended learning outcomes
Minimum requirements Students shall attain 50% overall and attain a minimum of a 25 % in the exam mark (10% of the overall mark). Lab and project reports have to be submitted to complete the subject and these have to be original and scoring at least 10 marks out of 30 (10 % of the overall mark) for each. Deadlines will be set for submission and late submissions will not be accepted without documented reasons. These reasons will exclude other study and work commitements.
Required texts Mohan et al, Power Electronics, Third Edition, John Wiley Publications
Recommended texts Other standard undergraduate texts may be useful - there are many.
References Mohan et al, Power Electronics, Third Edition, John Wiley Publications
Other resources UTSOnline Resources: Lecture Notes at UTS Online. Labs and other documentation will be posted online. Please look at site for announcements.
Assessment: faculty procedures and advice Special consideration Special consideration requests for the following are submitted and resolved through the UTS Special Consideration Process: www.sau.uts.edu.au/assessment/consideration
Special needs Students should email the subject coordinator as soon as possible (and prior to the assessment deadline) to indicate how their ability to meet an assessment component or requirement is impacted, and that they are seeking assistance through UTS Special Needs as detailed in Section 5.1.3 of Procedures for the Assessment of Coursework Subjects.
Academic integrity This subject outline should be read in conjunction with the information on assessment in both the course guide and the 24/02/2014 (Autumn 2014)
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UTS Policy and Procedures for the Assessment of Coursework Subjects, including details of assessment submission, late penalties, misconduct, plagiarism, etc.
Academic liaison officer Academic Liaison Officers (ALOs) are academic staff in each faculty who assist three groups of students: students with disabilities and ongoing illnesses; students who have difficulties in their studies because of their family commitments (e.g. being a primary carer for small children or a family member with a disability); and students who gained entry through the UTS Educational Access Scheme or Special Admissions. ALOs are responsible for determining alternative assessment arrangements for students with disabilities. Students who are requesting adjustments to assessment arrangements because of their disability or illness are requested to see a Disability Services Officer in the Special Needs Service before they see their ALO. The ALO for Engineering students is: Dr Bruce Moulton telephone +61 2 9514 2681 email
[email protected] The ALO for IT students is: Dr Julia Prior telephone +61 2 9514 4480 email
[email protected]
Support Improve your academic and English language skills: HELPS (Higher Education Language and Presentation Support) Service provides assistance with English language proficiency and academic language. Students who need to develop their written and/or spoken English should make use of the free services offered by HELPS, including academic language workshops, vacation intensive courses, drop-in consultations, individual appointments and Conversations@UTS (www.ssu.uts.edu.au/helps). HELPS is located in Student Services, on level 3 building 1. Phone 9514 9733.
Statement about assessment procedures and advice This subject outline must be read in conjunction with the policy and procedures for the assessment for coursework subjects, available at: www.gsu.uts.edu.au/policies/assessment-coursework.html
Querying marks/grades and final results If a student disagrees with a mark or a final result awarded by a marker: where a student wishes to query a mark, the deadline for a query during teaching weeks is 10 working days from the date of the return of the task to the student where a student wishes to query an examination result, the deadline is 10 working days from the official release of the final subject result. More information can be found at: https://my.feit.uts.edu.au/pages/course/student_policies_rules
Retention of student work The University reserves the right to retain the original or one copy of any work executed and/or submitted by a student as part of the course including, but not limited to, drawings, models, designs, plans and specifications, essays, programs, reports and theses, for any of the purposes designated in Rule 3.9.2 (www.gsu.uts.edu.au/rules/student/section-3.html#r3.9). Such retention is not to affect any copyright or other intellectual property right that may exist in such student work. Copies of student work may be retained for a period of up to five years for course accreditation purposes. Students are advised to contact their subject coordinator if they do not consent to the University retaining a copy of their work.
Statement on UTS email account Email from the University to a student will only be sent to the student's UTS email address. Email sent from a student to the University must be sent from the student's UTS email address. University staff will not respond to email from 24/02/2014 (Autumn 2014)
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to the University must be sent from the student's UTS email address. University staff will not respond to email from any other email accounts for currently enrolled students.
Disclaimer This outline serves as a supplement to the Faculty of Engineering and Information Technology Student Guide. On all matters not specifically covered in this outline, the requirements specified in the Student Guide apply. https://my.feit.uts.edu.au/modules/myfeit/downloads/StudentGuide_Online.pdf
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