Comb Co mbin inat atio iona nall Ci Circ rcui uits ts-- 1
Combinational Circuits • Two Two clas classses of logic ogic circ circui uits ts:: • Combinational Circuits • Sequential Circuits Combinati ationa onall circui circuitt consists of logic gates • A Combin • Output depends only on input Sequen enti tial al circ circui uitt consists of logic gates and memory • A Sequ • Output depends on current inputs and previous output (stored in memory) • Memory defines the state of the circuit.
Combinational Circuits • Two Two clas classses of logic ogic circ circui uits ts:: • Combinational Circuits • Sequential Circuits Combinati ationa onall circui circuitt consists of logic gates • A Combin • Output depends only on input Sequen enti tial al circ circui uitt consists of logic gates and memory • A Sequ • Output depends on current inputs and previous output (stored in memory) • Memory defines the state of the circuit.
Combinationall Circuits Combinationa
n inputs
Combinational Circuits
m outputs
A combinational circuit has: • n Boolea Boolean n inputs inputs (1 or or more) more) • m Boole Boolean an output outputs s (1 or or more) more) • logic gates gates mapping mapping the inputs inputs to the the outputs outputs
Designing Combinational Circuits • How to design a combinational circuit? • Use all the information and tools you learned Binary system, Boolean Algebra, K-Maps, etc.
• Follow the step-by-step procedure given next
Design Procedure 1.
Specification • Write a specification for the circuit if one is not already available • Specify/Label input and output 2. Formulation • Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification • Apply hierarchical design if appropriate 3. Optimization • Apply 2-level and multiple-level optimization (Boolean Algebra, K-Map, software) • Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters
Design Procedure (Cont.) 4.
Technology Mapping
• 5.
Map the logic diagram or netlist to the implementation technology selected (e.g. map into NANDs) Verification
• Verify the correctness of the final design manually or using simulation
Practical Considerations: • Cost of gates (Number) • Maximum allowed delay • Fanin/Fanout
Example 1 • Question: Design a circuit that has a 3-bit input and a single output (F) specified as follows: • F = 0, when the input is less than (5) 10 • F = 1, otherwise
• Solution: • Step 1 (Specification): • Label the inputs (3 bits) as X, Y, Z • X is the most significant bit, Z is the least significant bit
• The output (1 bit) is F: • F = 1 (101)2, (110)2, (111)2 • F = 0 other inputs
Example 1 (cont.) • Question: Design a circuit that has a 3-bit input and a single output (F) specified as follows: • F = 0, when the input is less than (5) 10 • F = 1, otherwise Solution: • Step 1 (Specification): • Label the inputs (3 bits) as X, Y, Z • X is the most significant bit, Z is the least significant bit • Output (1 bit) is F: • F = 1 (101)2, (110)2, (111)2 • F = 0 other inputs
Example 1 (cont.)
Step 3 (Optimization)
Step 2 (Formulation) Obtain Truth table
YZ X
00
01
11
10
0
0
0
0
0
1
0
1
1
1
X
Y
Z
F
0
0
0
0
0
0
1
0
0
1
0
0
X
0
1
1
0
Z
1
0
0
0
X
1
0
1
1
Y
1
1
0
1
1
1
1
1
Circuit Diagram
F = XZ + XY
F
Example 2 Question (BCD-to-Seven-Segment Decoder)
•
A seven-segment display is digital readout found in electronic devices like clocks, TVs, etc. • Made of seven light-emitting diodes (LED) segments; each segment is controlled separately.
•
A BCD-to-Seven-Segment decoder is a combinational circuit • Accepts a decimal digit in BCD (input) • Generates appropriate outputs for the segments to display the input decimal digit (output)
Example 2 (cont.)
• Step 1 (Specification): • 4 inputs (A, B, C, D) • 7 outputs (a, b, c, d, e, f, g) a b c d e f g
BCD-to-SevenSegment Decoder
A B C D
Example 2 (cont.) Step 2 (Formulation) BCD Input
7 Segment Decoder
Decimal
A
B
C
D
a
b
c
d
e
f
g
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
1
0
1
1
0
0
0
0
2
0
0
1
0
1
1
0
1
1
0
1
3
0
0
1
1
1
1
1
1
0
0
1
4
0
1
0
0
0
1
1
0
0
1
1
5
0
1
0
1
1
0
1
1
0
1
1
6
0
1
1
0
1
0
1
1
1
1
1
7
0
1
1
1
1
1
1
0
0
0
0
8
1
0
0
0
1
1
1
1
1
1
1
9
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
10-15
All Other Inputs
Invalid BCD codes = No Light
Example 2 (cont.) Step 3 (Optimization)
a
b
c
e
f
g
d
Example 2 (cont.)
Step 3 (Optimization) (cont.)
• a = A’C + A’BD + AB’C’ + B’C’D’ • b = A’B’ + A’C’D’ + A’CD + B’C’ • c = A’B + B’C’ + A’C’ + A’D • d = A’CD’ + A’B’C + B’C’D’+AB’C’+A’BC’D • e = A’CD’ + B’C’D’ • f = A’BC’ + A’C’D’ + A’BD’ + AB’C’ • g = A’CD’ + A’B’C + A’BC’ + AB’C’
Exercise: Draw the circuit
Arithmetic Circuit • Arithmetic Logic Unit (ALU) is main component that
performs arithmetic and logical operations on data in a digital computer
• Inside ALU circuit, arithmetic operations like addition and subtraction are done by using adders and gates • Half adder circuit is used to add two number of single binary bit • A full adder circuit is used to add three number of single bit • 2’s complement addition-subtraction circuits are basically used to perform addition-subtraction function
Arithmetic Circuit Half Adder A
Truth Table
Input Output Augend Addend Sum Carry A B S Co 0 0 1 1
0 1 0 1
0 1 1 0
0 0 0 1
B
1 1 K-Map for SUM Equation for sum =A B+ AB =A B Equation for Carry out, Co=A.B
A
A
B CO
The circuit realization
B
CO
Symbol for HA
Arithmetic Circuit Full Adder A full adder circuit has 3 inputs. The extra input into this adder circuit is called carry in input corresponding to the carry out from the previous bit position. A2A1A0=111 B2B1B0= 101 1100
A0 + B0=1+1=1 0 Carry in A1 +B1+1 =1+0+1=1 0 A2 +B2+1
Carry out=CO
=1+1+1=1 1
Arithmetic Circuit Full Adder A BCin Input
Output
A
B Cin
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Sum( )
0 1 1 0 1 0 0 1
1 Carry out Co 0 0 0 1 0 1 1 1
1
1
1
Equation for Sum = A BCin+ AB Cin +A B Cin+ABCin = A B Cin A BCin 1 1
1
1
Equation for Carry out, CO= AB+ACin+BCin
Arithmetic Circuit Full Adder A
B
Cin
CO
Full Adder Circuit realization
A B C
F.A
Full Adder symbol
CO
Arithmetic Circuit Full Adder using half adder • Full Adder can be constructed using two half adders • First half adder adds the two bits of the number and their sum is added to the carry in bit in another half adder
Input
Output HA#1 HA#2 Carry Out A B Cin 1 CO1 2 () CO2 CO AB AB 1Cin 1Cin CO1+CO2 00 00 01 01 10 10 11 11
0 1 0 1 0 1 0 1
0 0 1 1 1 1 0 0
0 0 0 0 0 0 1 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 0 0
0 0 0 1 0 1 1 1
Cin A B
1 HA#2 HA#1
CO1
2 () CO2 CO
A Full Adder Circuit using two Half Adder
Arithmetic Circuit Full Adder using half adder = A B Cin CO= CO1+CO2= AB+ (A B)Cin =AB+(A B+ AB) Cin =AB(1+ Cin)+A BCin + AB Cin where 1+Cin=1 =AB+AB Cin+A BCin + AB Cin =AB+AB Cin+ A B Cin +A BCin + AB Cin where AB Cin =AB+ACin(B+ B) +B Cin(A+ A) where B+ B=1 =AB+ACin+B Cin
Arithmetic Circuit
Binary Parallel Adder •
1 0 0 0
• •
• • • •
Carry in
0101 + 0110 1011 To add n-bit numbers: Use n Full-Adders in parallel The carries propagate as in addition by hand This is an example of a hierarchical design • The circuit is broken into small blocks
Parallel Adders C5
C 4 C3 C2 C1 A 4 A3 A2 A1 B 4 B3 B2 B1
CARRIES
S4
SUM
S3 S2 S1
Ar A r i t h m eti et i c Cir Ci r c u i t Binary Parallel Adder • To add n-bit numbers: • Use n Full-Adders in in pa parallel • carr carrie iess pro propa paga gate te as in addi additi tion on by hand hand
This adder is called ripple ripp le carry carry adder
Ar A r i t h m eti et i c Cir Ci r c u i t Ripple Adder Delay • Assu Assume me gate gate dela delay y = T, 8T to comp comput utee the the last last carr carry y
• Total otal delay delay = 8 + 1 = 9T 9T, 1 delay delay form form first first half half adder adder • Delay = (2n+1)T
Ar A r i t h m eti et i c Cir Ci r c u i t Parallel Adder A 4 B4
A3 B3
FA #3
FA #2
Cout
S4
A2 B2
A1 B1
FA #1
HA #1
S2
S1
S3
A - 4 bit Parallel Adder
A 4 B4
A3 B3
FA #3
FA #2
Cout
S4
A2 B2
A1 B1
FA #1
FA#1
S2
S1
S3
A - 4 bit Parallel Adder
C1
Arithmetic Circuit Parallel Adder B4 16
S4 COUT Cin GND B1 A1 15
14
13
12
11
S1
10
9
IC-7483 1
2
3
A4
S3
A3
4
5
B3
6
+5V S2
7
8
B2
A2
Fig.6: IC-7483
+5V 5
B8 B7 B6 B5 A 8 A 7 A 6
A5
16
10
12 14 Cout
4
7 11 1 3 8 IC-7483 15 2 6 9 S8
S7 S6
B4 +5V 5 13 Cin
16
B3
B2 B1 A4 A3 A2
4
7 Cin 13
12
S5 A 8-bit Adder using IC-7483
14 Cout
15 S4
11 1 3 8 IC-7483 2 6 9 S3 S2
S1
A1 10 13
Cin
Arithmetic Circuit Subtraction (2’s Complement) • How to build a subtractor using 2’s complement?
1
S = A + ( -B)
Arithmetic Circuit Half subtractor Consider A is minuend, B is subtrahend, Di is difference and Bo is borrow. Case-I Case-II Case-III Case-IV Bo 0 1 0 0 A 0 0 1 1 B 0 1 0 1 Di 0 -1 1 0
• Minus sign in case II indicates that a borrow from next higher is required
A
A B
Inputs Output A B Di Bo 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0
1
Di
B
BO
1 Di =A B+ AB =A B
BO= AB
A B
H.S
Di BO
Arithmetic Circuit Full Subtracter A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Bin 0 1 0 1 0 1 0 1
A Bin
D 0 1 1 0 1 0 0 1
A
BO 0 1 1 1 0 0 0 1
BBin
A BBin 1
1
1
1
1 1
1
B = AB + A Bin + BBin
D = A BBin + A B Bin +A B B0n+ ABBin =A B Bin
B
D
A B Bin BO
1
F.S
D BO
Arithmetic Circuit Full Subtracter Bin
A
D HS
A
A
D HS Bo
B
A B
B
B
Bin FS A B
Di Bo
Symbol for full adder
Di =ABBin Bin(AB)
Bo
AB+Bin(AB)
Arithmetic Circuit Adder/Subtracter Invert
Input Output A Invert Y 0 0 0 1 0 1
Y A
Controlled Inverter 1. when Invert=0 , then Y=A 2. When Invert=1, then Y= A.
0 1
AB
S or Di =A B Invert
1 1
1 0
Remark Y=A
Y= A
If Invert=0, then Y= AB and the circuit performs addition function.
Y A Half Adder/Half Subtracter
If Invert=0, then Y= AB and the circuit performs subtraction.
Arithmetic Circuit Subtraction (2’s Complement) • How to build a subtractor using 2’s complement?
1
S = A + ( -B)
Arithmetic Circuit 2's Complement Adder/Subtracter A4
A3
A2
A1 INVERT
A4
A3
A2
A1
A4
A3
A2
A1
A 4 B4
A 3 B3
If If
INVERT input =1 INVERT input =0
A2 B2
A1
B1 INVERT
Cin FA #4
Cout
S4
FA #3
S3
FA #2
S2
FA #1
S1
A - 4 bit 2's complement Adder/Subtracter
Arithmetic Circuit 2's Complement Adder/Subtracter A4 A3 A2 A1 B4
B3
B2
B1
1 2 4 5 9 10 12 13
INVERT IC-7486
3 +5V 5
1
6
8
11
3 8 Cin 10 16 4 13 IC-7483
7
13
12 14 Cout
15 S4
2 S3 S2
11
6
Cin
9 S1
2's complement Adder/Subtracter using IC-7483 and IC-7486
Combinational Circuits-II
Functional Blocks • Digital systems consists of many components (blocks) • Useful blocks needed in many designs • Arithmetic blocks • Decoders • Encoders • Multiplexers
Examples of MSI devices
Decoder
n
inputs
n-to-2n .
Decoder
. .
2n outputs
.
• Information is represented by binary codes • Decoding - the conversion of an n-bit input code to an m-bit output code with n <= m <= 2n such that each valid code word produces a unique output code • Circuits that perform decoding are called decoders • A decoder is a minterm generator
Decoder (Uses) •
Decode a 3-bit op-codes:
op0 op1 op2
3-to-8 Decoder
Add Sub And Xor Not Load Store Jump
•
Home automation:
C0 C1
2-to-4 Decoder
Light A/C Door Light-A/C
Decoder with Enable • A decoder can have an additional input signal called the enable which enables or disables the output generated by the decoder
n
inputs
n-to-2n .
Decoder Enable bit
. . .
2n outputs
2-to-4 Decoder • A 2-to-4 Decoder – 2 inputs (A1, A0) – 22 = 4 outputs (D3, D2, D1, D0)
2-to-4 Decoder • A 2-to-4 Decoder – 2 inputs (A1, A0) – 22 = 4 outputs (D3, D2, D1, D0) Truth Table
– A1
A0
D0
D1
D2
D3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
2-to-4 Decoder • A 2-to-4 Decoder – 2 inputs (A1, A0) – 22 = 4 outputs (D3, D2, D1, D0) Truth Table
– A1
A0
D0
D1
D2
D3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
2-to-4 Decoder with Enable Truth Table EN
A1
A0
D0
D1
D2
D3
0
X
X
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
2-to-4 Decoder with Enable Truth Table EN
A1
A0
D0
D1
D2
D3
0
X
X
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
3-to-8 Decoder
A0 A1 A2
D0 D1 D2 3-to-8 D3 Decoder D4 D5 D6 D7
3-to-8 Decoder A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 A2
D0 D1 D2 3-to-8 D3 Decoder D4 D5 D6 D7
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
3-to-8 Decoder
A0 A1 A2
D0 D1 D2 3-to-8 D3 Decoder D4 D5 D6 D7
3-to-8 Decoder (using 2 2-to-4 decoders)
A0 A1 A2
D0 D1 D2 3-to-8 D3 Decoder D4 D5 D6 D7
A0 A1
2-to-4 Decoder E
D0 D1 D2 D3
A2
A0 A1
2-to-4 Decoder E
D4 D5 D6 D7
Encoder 2n inputs
. . .
2n-to-n Encoder
.
n
outputs
• Encoding - the opposite of decoding - the conversion of an m bit input code to a n-bit output code with n m 2n such that each valid code word produces a unique output code • Circuits that perform encoding are called encoders • An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values • Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.
8-to-3 Encoder D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
•
Description:
•
23 = 8 inputs, 3 outputs
•
one input =1, others = 0’s
•
Each input generate unique binary code
8-to-3 Encoder (truth table) inputs D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (truth table) inputs 1 0 0 0 0 0 0 0
D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0 0 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (truth table) inputs 0 1 0 0 0 0 0 0
D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 0 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (truth table) inputs 0 0 0 0 0 1 0 0
D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 0 1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (truth table) inputs 0 0 0 0 0 0 0 1
D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 1 1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (equations) inputs D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
Output equations: A0 = ? A1 = ? A2 = ?
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
8-to-3 Encoder (equations) inputs D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
Output equations: A0 = D1 + D3 + D5 + D7 A1 = ? A2 = ?
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0
0
0
0
0
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1
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8-to-3 Encoder (equations) inputs D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
Output equations: A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = ?
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0
0
0
0
0
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1
0
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8-to-3 Encoder (equations) inputs D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
Output equations: A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7
outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0
0
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8-to-3 Encoder (circuit) D0 D1 D2 D3 8-to-3 A0 D4 Encoder A1 A2 D5 D6 D7
Output equations: A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7
D1 D3 D5 D7
A 0
D2 D3 D6 D7
A 1
D4 D5 D6 D7
A 2
Multiplexers • A combinational circuit • Has a single output • Directs one of 2n input to the output • Choosing which input is done using n select lines
2n inputs
2n x 1 MUX
n select lines
one output
2x1 MUX • A 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1 select line D0 D1
2x1 MUX
Y
S0
• Y=D0 for S0=0, and Y=D1 for S0=1 • Minimizing will result in: Y = S0’.D0 + S0.D1 • Exercise: Draw the circuit?
2x1 MUX • A 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1 select line D0 D1
2x1 MUX
Y
S0
• Y=D0 for S0=0, and Y=D1 for S0=1 • Minimizing will result in: Y = S0’.D0 + S0.D1 • Exercise: Draw the circuit?
4x1 MUX • • • • • •
A 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select Lines (S0, S1) The output for different select values is defined as: D0 S0S1 = 00, Y = D0 S0S1 = 01, Y = D1 D1 4x1 S0S1 = 10, Y = D2 D2 MUX S0S1 = 11, Y = D3
• • •
Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3 The output Y depends on the minterms of the Select lines Exercise: Draw the circuit?
D3
S1 S0
Y
4x1 MUX • • • • • •
A 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select Lines (S0, S1) The output for different select values is defined as: D0 S0S1 = 00, Y = D0 S0S1 = 01, Y = D1 D1 4x1 S0S1 = 10, Y = D2 D2 MUX S0S1 = 11, Y = D3
•
Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3
•
The output Y depends on the minterms of the Select lines
•
Exercise: Draw the circuit?
D3
S1 S0
Y
4x1 MUX
Quad 2x1 MUX • A MUX for two 4-bit numbers.
A0
• Has a 4-bit output and a single select line
A2
A1
A3
• Y = A If S0 = 0
B0
• Y = B if S0 = 1
B1
QUAD 2X1 MUX
B2 B3
S0
Y0 Y1 Y2 Y3
Quad 2x1 MUX • Can be built using four 2x1 MUXes A0 B0
2x1 MUX
Y0
A1 B1
S0 A2 B2
2x1 MUX S0
2x1 MUX
Y1
S0 Y2
A3 B3
2x1 MUX S0
Y3
DeMultiplexer • Performs the inverse operation of a MUX • It has one input and 2n outputs • The input is passed to one of the outputs based on the n select line
one input
1 x 2n DeMUX
n select lines
2n outputs
1x2 DeMUX E
1x2 DeMUX
D0 D1
S
The circuit has an input E, the outputs are given by: D0 = E, if S=0 D1 = E, if S=1
D0 = S E D1 = S E
1x4 DeMUX E
1x4 DeMUX
D0 D1 D2 D3
S1 S0
• The circuit has an input E, the outputs are given by: •
D0 = E, if S0S1=00
D0 = S1’S0’ E
•
D1 = E, if S0S1=01
D1 = S1’S0 E
•
D2 = E, if S0S1=10
D2 = S1S0’ E
•
D3 = E, if S0S1=11
D3 = S1S0 E
DeMUX vs Decoder E
1x4 DeMUX
D0 D1 D2 D3
S1 S0
• A 1x4 DeMUX is equivalent to a 2x4 Decoder with an Enable • Think of S1S0 a the decoder’s input • Think of E as the decoder’s enable
• In general, a DeMux is equivalent to a Decoder with an Enable
DeMUX vs Decoder 2x4 Decoder Truth Table EN
A1
A0
D0
D1
D2
D3
0
X
X
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
DeMUX vs Decoder 2x4 Decoder Truth Table EN
A1
A0
D0
D1
D2
D3 Data/
0
X
X
0
0
0
0
S 1/
1
0
0
1
0
0
0
S 0/
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
• To convert a 2x4 Decoder with an Enable to a 1x4 DeMux: • Assign DeMux’s input (actual data) to EN • Assign DeMux’s selection lines (S1,S0) to the inputs A1, A0
